Device Visibility
Def Port-Mapped I/O (PMIO) The device is accessible in a dedicated address space, separate from the address space of memory. I/O devices have a separate address space from general memory, typically accomplished by extra “I/O” pins on the CPU’s physical interface. Because the address space for I/O is isolated from that for main memory, this is sometimes referred to as isolated I/O.
Def Memory-Mapped I/O (MMIO) I/O devices and memory share the same address space. Each I/O device has its own reserved block of memory. Data transfers to and from the I/O device involve moving bytes to and from the memory address that is mapped to the device. MMIO is like using regular load/store instructions from the programmer’s perspective.
Reading Data
Def Programmed I/O Each data item transfer is initiated by an instruction in the program, involving the CPU for every transaction. The term can refer to either memory-mapped I/O (MMIO) or port-mapped I/O (PMIO). However, since CPU is much faster than the I/O device, for large data transfers (for example, reading a video file from disk), we would like to free up the CPU to do other things while transfer happens in parallel.
Def Direct-Memory Access (DMA) CPU offloads the execution of tedious I/O instructions to a dedicated chip called DMA controller, where CPU provides the DMA controller with
- The location of the bytes to be transferred
- The number of bytes to be transferred
- The destination memory address
And DMA controller will place the data in memory and interrupts the CPU.
Event Notification
Def Polled I/O CPU monitors a control/status register associated with a port. When a byte arrives in the port, a bit in the control register is set. The CPU eventually polls and notices that the “data ready” control bit is set. The CPU resets the control bit, retrieves the byte, and processes it. Finally, the CPU resumes polling the register as before.
Def Interrupt-driven I/O CPU is not held up from doing other things. Interrupts are asynchronous signals, the devices tell the CPU when they have data to send. The CPU proceeds with other tasks until a device requesting service sends an interrupt to the CPU. Concretely, communication between many interrupt-enabled devices and CPU is handled via an interrupt controller. Once the circuit recognizes an interrupt signal from any device, it raises a single interrupt signal that activates a control line on the system bus. Control line feeds directly into a pin on the CPU chip.
I/O Devices
Def Character I/O devices process one byte (or character) at a time. e.g. Modems, keyboards, and mice
Def Block I/O devices handle bytes in groups e.g. Most mass storage devices (disk and tape)
Prop Block I/O systems are most efficiently connected through interrupt-driven DMA.
Def Device driver is the software that handles the details of I/O transfer granularity and I/O-related instructions in general
Bus Technology
Def Bus Bus is a collection of wires to transfer signals (address, data, control) between sender and receiver. It can do serial transmissions(i.e. one bit at a time) or parallel transmissions(i.e. multiple bits in parallel)
Amdahl’s Law
Thrm Amdahl’s Law
The overall performance of a system is a result of the interaction of all of its components. And system performance is most effectively improved when the performance of the most heavily used components is improved.